(Ebook) The VLSI Handbook by Wai-Kai Chen ISBN 9780849341991, 084934199X

(Ebook) The VLSI Handbook by Wai-Kai Chen ISBN 9780849341991, 084934199X

Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and other resources-such as software, databases, standards, and seminars-points toward more in-depth information.Section I VLSI TechnologyBipolar TechnologyCMOS/BiCMOS TechnologySilicon-on-Insulator TechnologySiGe HBT TechnologySilicon Carbide TechnologyPassive ComponentsPower IC TechnologiesMicroelectronics PackagingMultichip Module TechnologiesSection II Devices and Their ModelsBipolar Junction Transistor CircuitsRF Passive IC ComponentsCMOS FabricationAnalog Circuit SimulationInterconnect Modeling and SimulationSection III Low Power Electronics and DesignSystem-Level Power Management: An OverviewCommunication-Based Design for Nanoscale SoCsPower-Aware Architectural SynthesisDynamic Voltage Scaling for Low-Power Hard Real-Time SystemsLow-Power Microarchitecture Techniques and Compiler Design TechniquesArchitecture and Design Flow Optimizations for Power-Aware FPGAsTechnology Scaling and Low-Power Circuit DesignSection IV AmplifiersCMOS Amplifier DesignBipolar Junction Transistor AmplifiersHigh-Frequency AmplifiersOperational Transconductance AmplifiersSection V Logic CircuitsExpressions of Logic FunctionsBasic Theory of Logic FunctionsSimplification of Logic ExpressionsBinary Decision DiagramsLogic Synthesis with AND and OR Gates in Two LevelsSequential Networks 32 Logic Synthesis with AND and OR Gates in Multi-LevelsLogic Properties of Transistor CircuitsLogic Synthesis with NAND (or NOR) Gates in Multi-LevelsLogic Synthesis with a Minimum Number of Negative GatesLogic Synthesizer with Optimizations in Two PhasesLogic Synthesizer by the Transduction MethodEmitter-Coupled LogicCMOSPass TransistorsAddersMultipliersDividersFull-Custom and Semi-Custom DesignProgrammable Logic DevicesGate ArraysField-Programmable Gate ArraysCell-Library Design ApproachComparison of Different Design ApproachesSection VI Memory, Registers and System TimingSystem TimingROM/PROM/EPROM 52 SRAMEmbedded MemoryFlash MemoriesDynamic Random Access MemoryContent-Addressable MemoryLow-Power Memory CircuitsSection VII Analog CircuitsNyquist-Rate ADC and DACOversampled Analog-to-Digital and Digital-to-Analog ConvertersRF Communication CircuitsPLL CircuitsSwitched-Capacitor FiltersSection VIII Microprocessor and ASICTiming and Signal Integrity AnalysisMicroprocessor Design VerificationMicroprocessor Layout MethodArchitectureLogic Synthesis for Field Programmable Gate Array (FPGA) TechnologySection IX Testing of Digital SystemsDesign for Testability and Test ArchitecturesAutomatic Test Pattern Generation 70 Built-In Self-TestSection X Compound Semiconductor Integrated Circuit TechnologyCompound Semiconductor MaterialsCompound Semiconductor Devices for Analog and Digital CircuitsCompound Semiconductor RF CircuitsHigh-Speed Circuit Design PrinciplesSection XI Design AutomationInternet-Based Micro-Electronic Design Automation (IMEDA) FrameworkSystem-Level DesignPerformance Modeling and Analysis Using VHDL and SystemCEmbedded Computing Systems and Hardware/SoftwareDesign Automation Technology RoadmapSection XII VLSI Signal ProcessingComputer Arithmetic for VLSI Signal ProcessingVLSI Architectures for JPEG 2000 EBCOT: Design Techniques and ChallengesVLSI Architectures for Forward Error-Control DecodersAn Exploration of Hardware Architectures for Face DetectionMultidimensional Logarithmic Number SystemSection XIII Design LanguagesLanguages for Design and Implementation of HardwareSystem Level Design LanguagesRT Level Hardware Description with VHDLRegister Transfer Level Hardware Description with VerilogRegister-Transfer Level Hardware Description with SystemCSystem VerilogVHDL-AMS Hardware Description LanguageVerification LanguagesASIC and Custom IC Cell Information RepresentationTest LanguagesTiming Description LanguagesHDL-Based Tools and Environments