(Ebook) Switching and Finite Automata Theory 3rd edition by Zvi Kohavi, Niraj Jha 0521857481 9780521857482

(Ebook) Switching and Finite Automata Theory 3rd edition by Zvi Kohavi, Niraj Jha 0521857481 9780521857482

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Product details:

ISBN-10 :  0521857481 

ISBN-13 :  9780521857482

Author:  Zvi Kohavi, Niraj K. Jha 

Understand the structure, behaviour, and limitations of logic machines with this thoroughly updated third edition. Many new topics are included, such as CMOS gates, logic synthesis, logic design for emerging nanotechnologies, digital system testing, and asynchronous circuit design, to bring students up-to-speed with modern developments. The intuitive examples and minimal formalism of the previous edition are retained, giving students a text that is logical and easy to follow, yet rigorous. Kohavi and Jha begin with the basics, and then cover combinational logic design and testing, before moving on to more advanced topics in finite-state machine design and testing. Theory is made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.

Switching and Finite Automata Theory 3rd table of contents:

Part 1: Preliminaries
1. Number systems and codes
1.1 Number systems
1.2 Binary codes
1.3 Error detection and correction
Notes and references
Problems
2. Sets, relations, and lattices
2.1 Sets
2.2 Relations
2.3 Partially ordered sets
2.4 Lattices
Notes and references
Problems
Part 2: Combinational logic
3. Switching algebra and its applications
3.1 Switching algebra
3.2 Switching functions
3.3 Isomorphic systems
3.4 Electronic-gate networks
*3.5 Boolean algebras
Notes and references
Problems
4. Minimization of switching functions
4.1 Introduction
4.2 The map method
4.3 Minimal functions and their properties
4.4 The tabulation procedure for the determination of prime implicants
4.5 The prime implicant chart
4.6 Map-entered variables
4.7 Heuristic two-level circuit minimization
4.8 Multi-output two-level circuit minimization
Notes and references
Problems
5. Logic design
5.1 Design with basic logic gates
5.2 Logic design with integrated circuits
5.3 NAND and NOR circuits
5.4 Design of high-speed adders
5.5 Metal-oxide semiconductor (MOS) transistors and gates
5.6 Analysis and synthesis of MOS networks
Notes and references
Problems
6. Multi-level logic synthesis
6.1 Technology-independent synthesis
6.2 Technology mapping
Notes and references
Problems
7. Threshold logic for nanotechnologies
7.1 Introductory concepts
7.2 Synthesis of threshold networks
Notes and references
Problems
8. Testing of combinational circuits
8.1 Fault models
8.2 Structural testing
8.3 I[sub(DDQ)] testing
8.4 Delay fault testing
8.5 Synthesis for testability
8.6 Testing for nanotechnologies
Notes and references
Problems
Part 3: Finite-state machines
9. Introduction to synchronous sequential circuits and iterative networks
9.1 Sequential circuits – introductory example
9.2 The finite-state model – basic definitions
9.3 Memory elements and their excitation functions
9.4 Synthesis of synchronous sequential circuits
9.5 An example of a computing machine
9.6 Iterative networks
Notes and references
Problems
10. Capabilities, minimization, and transformation of sequential machines
10.1 The finite-state model – further definitions
10.2 Capabilities and limitations of finite-state machines
10.3 State equivalence and machine minimization
10.4 Simplification of incompletely specified machines
Notes and references
Problems
11. Asynchronous sequential circuits
11.1 Modes of operation
11.2 Hazards
11.3 Synthesis of SIC fundamental-mode circuits
11.4 Synthesis of burst-mode circuits
Notes and references
Problems
12. Structure of sequential machines
12.1 Introductory example
12.2 State assignments using partitions
12.3 The lattice of closed partitions
12.4 Reduction of the output dependency
12.5 Input independency and autonomous clocks
12.6 Covers, and the generation of closed partitions by state splitting
12.7 Information flow in sequential machines
12.8 Decomposition
*12.9 Synthesis of multiple machines
Notes and references
Problems
13. State-identification experiments and testing of sequential circuits
13.1 Experiments
13.2 Homing experiments
13.3 Distinguishing experiments
13.4 Machine identification
13.5 Checking experiments
*13.6 Design of diagnosable machines
13.7 Alternative approaches to the testing of sequential circuits
13.8 Design for testability
13.9 Built-in self-test (BIST)
Appendix 13.1 Bounds on the length of synchronizing sequences
Appendix 13.2 A bound on the length of distinguishing sequences
Notes and references
Problems
14. Memory, definiteness, and information losslessness of finite automata
14.1 Memory span with respect to input–output sequences (finite-memory machines)
14.2 Memory span with respect to input sequences (definite machines)
14.3 Memory span with respect to output sequences
14.4 Information-lossless machines
*14.5 Synchronizable and uniquely decipherable codes
Appendix 14.1 The least upper bound for information losslessness of finite order
Notes and references
Problems
15. Linear sequential machines
15.1 Introduction
15.2 Inert linear machines
15.3 Inert linear machines and rational transfer functions
15.4 The general model
15.5 Reduction of linear machines
15.6 Identification of linear machines
15.7 Application of linear machines to error correction
Appendix 15.1 Basic properties of finite fields
Appendix 15.2 The Euclidean algorithm
Notes and references
Problems
16. Finite-state recognizers
16.1 Deterministic recognizers
16.2 Transition graphs
16.3 Converting nondeterministic into deterministic graphs
16.4 Regular expressions
16.5 Transition graphs recognizing regular sets
16.6 Regular sets corresponding to transition graphs
*16.7 Two-way recognizers

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