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0 reviewsProvides a comprehensive set of techniques to enhance all key aspects of a Virtual Prototype (VP)-based design flow
Includes automated formal verification methods and advanced coverage-guided testing techniques, tailored for SystemC-based VPs
Describes efficient, coverage-guided test generation methods for VP-based functional and non-functional software (SW) analysis and verification
Includes correspondence analyses to utilize information between different abstraction levels in the design flow
Uses several VP and SW verification case-studies that target the modern RISC-V ISA
4.6
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