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ISBN 10: 0521872448
ISBN 13: 9780521872447
Author: Peter A Beerel, Recep O Ozdag, Marcos Ferretti
Create low power, higher performance circuits with shorter design times using this practical guide to asynchronous design. This practical alternative to conventional synchronous design enables performance close to full-custom designs with design times that approach commercially available ASIC standard cell flows. It includes design trade-offs, specific design examples, and end-of-chapter exercises. Emphasis throughout is placed on practical techniques and real-world applications, making this ideal for circuit design students interested in alternative design styles and system-on-chip circuits, as well as circuit designers in industry who need new solutions to old problems.
1 Introduction
1.1 Synchronous design basics
1.2 Challenges in synchronous design
1.3 Asynchronous design basics
1.4 Asynchronous design flows
1.5 Potential advantages of asynchronous design
1.6 Challenges in asynchronous design
1.7 Organization of the book
2 Channel-based asynchronous design
2.1 Asynchronous channels
2.2 Sequencing and concurrency
2.3 Asynchronous memories and holding state
2.4 Arbiters
2.5 Design examples
2.6 Exercises
3 Modeling channel-based designs
3.1 Communicating sequential processes
3.2 Using asynchronous-specific languages
3.3 Using software programming languages
3.4 Using existing hardware design languages
3.5 Modeling channel communication in Verilog
3.6 Implementing VerilogCSP macros
3.7 Debugging in VerilogCSP
3.8 Summary of VerilogCSP macros
3.9 Exercises
4 Pipeline performance
4.1 Block metrics
4.2 Linear pipelines
4.3 Pipeline loops
4.4 Forks and joins
4.5 More complex pipelines
4.6 Exercises
5 Performance analysis and optimization
5.1 Petri nets
5.2 Modeling pipelines using channel nets
5.3 Performance analysis
5.4 Performance optimization
5.5 Advanced topic: stochastic performance analysis
5.6 Exercises
6 Deadlock
6.1 Deadlock caused by incorrect circuit design
6.2 Deadlock caused by architectural token mismatch
6.3 Deadlock caused by arbitration
7 A taxonomy of design styles
7.1 Delay models
7.2 Timing constraints
7.3 Input–output mode versus fundamental mode
7.4 Logic styles
7.5 Datapath design
7.6 Design flows: an overview of approaches
7.7 Exercises
8 Synthesis-based controller design
8.1 Fundamental-mode Huffman circuits
8.2 STG-based design
8.3 Exercises
9 Micropipeline design
9.1 Two-phase micropipelines
9.2 Four-phase micropipelines
9.3 True-four-phase pipelines
9.4 Delay line design
9.5 Other micropipeline techniques
9.6 Exercises
10 Syntax-directed translation
10.1 Tangram
10.2 Handshake components
10.3 Translation algorithm
10.4 Control component implementation
10.5 Datapath component implementations
10.6 Peephole optimizations
10.7 Self-initialization
10.8 Testability
10.9 Design examples
10.10 Summary
10.11 Exercises
11 Quasi-delay-insensitive pipeline templates
11.1 Weak-conditioned half buffer
11.2 Precharged half buffer
11.3 Precharged full buffer
11.4 Why input-completion sensing?
11.5 Reduced-stack precharged half buffer (RSPCHB)
11.6 Reduced-stack precharged full buffer (RSPCFB)
11.7 Quantitative comparisons
11.8 Token insertion
11.9 Arbiter
11.10 Exercises
12 Timed pipeline templates
12.1 Williams’ PS0 pipeline
12.2 Lookahead pipelines overview
12.3 Dual-rail lookahead pipelines
12.4 Single-rail lookahead pipelines
12.5 High-capacity pipelines (single-rail)
12.6 Designing non-linear pipeline structures
12.7 Lookahead pipelines (single-rail)
12.8 Lookahead pipelines (dual-rail)
12.9 High-capacity pipelines (single-rail)
12.10 Conditionals
12.11 Loops
12.12 Simulation results
12.13 Summary
13 Single-track pipeline templates
13.1 Introduction
13.2 GasP bundled data
13.3 Pulsed logic
13.4 Single-track full-buffer template
13.5 STFB pipeline stages
13.6 STFB standard-cell implementation
13.7 Back-end design flow and library development
13.8 The evaluation and demonstration chip
13.9 Conclusions and open questions
13.10 Exercises
14 Asynchronous crossbar
14.1 Fulcrum's Nexus asynchronous crossbar
14.2 Clock domain converter
15 Design example: the Fano algorithm
15.1 The Fano algorithm
15.2 The asynchronous Fano algorithm
15.3 An asynchronous semi-custom physical design flow
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Tags: Peter A Beerel, Recep O Ozdag, Marcos Ferretti, Designer, Asynchronous
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